A dynamic circuit is a circuit whose output is triggered by a clock signal applied to the dynamic circuit. A dynamic circuit operates in two different modes, namely an evaluation mode and a pre-charge mode, depending on whether the value of the clock signal, applied to the dynamic circuit, has a logic high value (in other words, a “1”) or a logic low value (in other words, a “0”).
When the clock signal applied to the dynamic circuit has a logic high value, the dynamic circuit is in evaluation mode. In evaluation mode, the logic of the dynamic circuit is evaluated using the inputs to the dynamic circuit. Thus, when a dynamic circuit is in evaluation mode, the output of the dynamic circuit depends upon the evaluation of the logic of the dynamic circuit using the inputs applied to the dynamic circuit.
When the clock signal applied to the dynamic circuit has a logic low value, the dynamic circuit is in pre-charge mode. In pre-charge mode, the logic of the dynamic circuit is not evaluated. The output of a dynamic circuit in pre-charge mode is driven to a logical low value, since the logic of the dynamic circuit is not being evaluated.
FIGS. 1A and 1B are both illustrations of illustrative dynamic circuits. When the dynamic circuit 100 of FIG. 1A is in pre-charge mode, the clock signal will have a logic low value. As a result, the dynamic node 104 will be driven to a logic high value because the transistor 110 will be turned on, thereby coupling the dynamic node 104 to voltage source 112. This causes the output signal 106 of the dynamic circuit 100 to be driven to a logic low value (due to inverter 108).
During the evaluation mode of the dynamic circuit 100, the clock signal will have a logic high value, which turns off transistor 110. Since transistor 110 is turned off, the dynamic node 104 is not connected to voltage source 112 when the dynamic circuit 100 is in evaluation mode.
If, during evaluation mode, the logic of the pull down network (PDN) 102 is evaluated to a logic high, the PDN 102 will discharge the dynamic node 104 and pull the voltage of the dynamic node 104 down to a logic low voltage (to ground). This causes the output signal 106 of the dynamic circuit 100 to have a logic high value due to inverter 108.
On the other hand, if during evaluation mode, the PDN 102 is not evaluated to a logic high value, then the PDN 102 will not drive the dynamic node 104 to a logic low voltage since the dynamic node 104 will not be connected to ground 114. Rather, the PDN 102 simply leaves the voltage of the dynamic node 104 as is. The charge that was imposed on the dynamic node 104 during the pre-charge mode is relied upon to keep the dynamic node 104 at a logic high level. When the voltage of the dynamic node 104 has a logic high value, the output of the dynamic circuit 100 has a logic low value because of inverter 108. As the above discussion shown, when the dynamic circuit is in evaluation mode and the PDN 102 is evaluated as having a logic low value, nothing is driving the dynamic node 104. Thus, under these conditions, the dynamic node 104 is a floating node.
While the dynamic node 104 is a floating node, current may leak from the dynamic node 104 through the PDN 102. If enough current leaks from the dynamic node 104 through the PDN 102, the resulting reduction in the charge of the dynamic node 104 may cause the dynamic node 104 to cross over from a logic high level to a logic low level. This would, in turn, cause the output of the dynamic circuit to change from having a logic low value to a logic high value. If this happens, a logical failure results because the output signal 106 should have been a logic low value.
The keeper transistor 152 of FIG. 1B prevents this situation from occurring in dynamic circuit 150. As shown in FIG. 1B, if the PDN 154 does not discharge the dynamic node 156, then the dynamic node 156 will retain a logical high voltage due to the keeper transistor 152, and the output signal 158 of the dynamic circuit will remain at logic low voltage. When the keeper transistor 152 is turned on (as is the case when the output signal 158 has a logic low value), the keeper transistor 152 provides an amount of current to the dynamic node 156 to compensate the current leaking from the dynamic node 156. Thus, the keeper transistor 152 serves to retain the pre-charged voltage level at the dynamic node 156 of dynamic circuit 150 when the dynamic circuit 150 is in evaluation mode.
The size of the transistor can directly impact the delay of the circuit. Thus, it is desirable to use a keeper transistor whose size is large enough that the keeper transistor provides enough current to the dynamic node to compensate for the current leaking from the dynamic node, but not so large as to unduly slow down the evaluation of the dynamic circuit, as larger keeper transistors require additional time to transition from being turned on and off.
Traditionally, to determine the size of a keeper transistor, an arbitrary initial size is chosen by a circuit designer for the keeper transistor. The initial size of the keeper transistor may be based on the size of the keeper transistor that the circuit designer feels is a good starting point based on the experience of the circuit designer in view of the characteristics of the dynamic circuit. After selecting the initial size of the keeper transistor, the circuit designer may perform a simulation of the dynamic circuit using the initial selected keeper transistor size to ensure that the selected size of the keeper transistor causes the dynamic circuit to perform within a specified set of requirements, such as a requirement that the voltage level of the dynamic node remains at some specified level when the dynamic circuit is in the evaluation mode.
If a chosen size of the keeper transistor does not perform as expected, then the circuit designer may fine-tune the size of the keeper transistor by (a) choosing a new size of the keeper transistor and (b) performing another simulation of the dynamic circuit using the new size of the keeper transistor. The circuit designer may repeat these steps as necessary to ensure that the chosen size of the keeper transistor causes the dynamic circuit to perform within a specified set of requirements. Unfortunately, such an approach requires numerous iterations.